`ifndef MEM
`define MEM


`include "../core/defines.v"

module mem(
       input  wire 		   clk  	,
	   input  wire 		   rstn  	,
       input  wire[3:0]    wen  	,
	   input  wire[32-1:0] waddr_i ,
	   input  wire[32-1:0] wdata_i ,
	   input  wire 		   ren 		,
	   input  wire[32-1:0] raddr_i ,
       output wire[32-1:0] rdata_o	
);

wire[11:0] waddr = waddr_i[13:2];
wire[11:0] raddr = raddr_i[13:2];

// 字节0
dual_ram #(
		.DATA_WIDTH(8),
		.ADDR_WIDTH(12),
		.MEM_NUM(4096)
)
ram_byte0
(
	.clk     	(clk        	),
	.rstn    	(rstn        	),
	.wen     	(wen[0] 		),
	.waddr_i 	(waddr 		),
	.wdata_i 	(wdata_i[7:0]	),
	.ren     	(ren			),
	.raddr_i 	(raddr 		),
	.rdata_o 	(rdata_o[7:0]	)
);
// 字节1
dual_ram #(
		.DATA_WIDTH(8),
		.ADDR_WIDTH(12),
		.MEM_NUM(4096)
)
ram_byte1
(
	.clk     	(clk        	),
	.rstn    	(rstn        	),
	.wen     	(wen[1]			),
	.waddr_i 	(waddr 		),
	.wdata_i 	(wdata_i[15:8]	),
	.ren     	(ren			),
	.raddr_i 	(raddr 		),
	.rdata_o 	(rdata_o[15:8]	)
);	
// 字节2
dual_ram #(
		.DATA_WIDTH(8),
		.ADDR_WIDTH(12),
		.MEM_NUM(4096)
)
ram_byte2
(
	.clk    	(clk        	),
	.rstn   	(rstn        	),
	.wen    	(wen[2]			),
	.waddr_i	(waddr 		),
	.wdata_i	(wdata_i[23:16]),
	.ren    	(ren			),
	.raddr_i	(raddr 		),
	.rdata_o	(rdata_o[23:16])
);
// 字节3
dual_ram #(
		.DATA_WIDTH(8),
		.ADDR_WIDTH(12),
		.MEM_NUM(4096)
)
ram_byte3
(
	.clk    	(clk        	),
	.rstn   	(rstn        	),
	.wen    	(wen[3]			),
	.waddr_i	(waddr 		),
	.wdata_i	(wdata_i[31:24]),
	.ren    	(ren			),
	.raddr_i	(raddr 		),
	.rdata_o	(rdata_o[31:24])
);	
	
endmodule


`endif // MEM